干旱区生态环境知识资源中心(Arid): Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs

Arid

DOI	10.1145/3403702
	Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs
	Tang, Qi; Wang, Zhe; Guo, Biao; Zhu, Li-Hua; Wei, Ji-Bo
通讯作者	Tang, Q
来源期刊	ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS
ISSN	1936-7406
EISSN	1936-7414
出版年	2020
卷号	13 期号:3
英文摘要	Field programmable gate array (FPGA) is ubiquitous nowadays and is applied to many areas. Dynamic partial reconfiguration (DPR) is introduced to most modern FPGAs, enabling changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. However, delivering the powerful capacity of the DPR FPGA to the user depends on the efficient partitioning and scheduling technology. This article proposes the module merging technique for the partitioning and scheduling problem to reduce the reconfiguration overhead and improve the schedule performance. An exact approach based on the integer linear programming (ILP) for the partitioning and scheduling problem with module merging is proposed. The ILP-based approach is capable of solving the problem optimally, and can be used to further improve the performance of schedules produced by other non-optimal algorithms; however, it is time-consuming to solve large-scale problems. Therefore, a K-sliced-ILP algorithm based on the methodology of divide-arid-conquer is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. Experiments are carried out with a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.
英文关键词	Dynamic partial reconfiguration partitioning scheduling integer linear programming
类型	Article
语种	英语
收录类别	SCI-E
WOS记录号	WOS:000583746200006
WOS关键词	ARCHITECTURES ; PARALLELISM ; GRAPHS ; FLOW
WOS类目	Computer Science, Hardware & Architecture
WOS研究方向	Computer Science
资源类型	期刊论文
条目标识符	http://119.78.100.177/qdio/handle/2XILL650/327199
作者单位	[Tang, Qi; Wang, Zhe; Guo, Biao; Zhu, Li-Hua; Wei, Ji-Bo] Natl Univ Def Technol, 109 Deya Rd, Changsha 410073, Hunan, Peoples R China; [Wang, Zhe; Guo, Biao; Zhu, Li-Hua] Hunan Univ, 2 South Lushan Rd, Changsha 410082, Hunan, Peoples R China
推荐引用方式 GB/T 7714	Tang, Qi,Wang, Zhe,Guo, Biao,et al. Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs[J],2020,13(3).
APA	Tang, Qi,Wang, Zhe,Guo, Biao,Zhu, Li-Hua,&Wei, Ji-Bo.(2020).Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs.ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS,13(3).
MLA	Tang, Qi,et al."Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs".ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 13.3(2020).