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DOI | 10.1109/VLSIT.2002.1015384 |
A highly manufacturable 110nm DRAM technology with 8F(2) vertical transistor cell for 1Gb and beyond | |
Akatsu, H; Weis, R; Cheng, K; Seitz, M; Kim, MS; Ramachandran, R; Dyer, T; Kim, B; Kim, DK; Malik, R; Strane, J; Goebel, T; Kwon, OJ; Sung, CY; Parkinson, P; Wilson, K; McStay, I; Chudzik, M; Dobuzinsky, D; Jacunski, M; Ransom, C; Settlemyer, K; Economikos, L; Simpson, A; Knorr, A; Naeem, M; Stojakovic, G; Robl, W; Gluschenkov, O; Liegl, B; Wu, CH; Wu, Q; Li, WK; Choi, CJ; Arnold, N; Joseph, T; Varn, K; Weybright, M; McStay, K; Kang, WT; Li, Y![]() | |
通讯作者 | Akatsu, H |
会议名称 | Symposium on VLSI Technology |
会议日期 | JUN 11-13, 2002 |
会议地点 | HONOLULU, HI |
英文摘要 | This paper describes a 110 nm half-pitch DRAM technology utilizing an 8F(2) vertical transistor trench cell and optimized for ease of manufacturing and scaling. All four critical lithography steps are regular patterns in the array. High performance is provided through the use of tungsten Word-Lines, tungsten Bit-Lines, arid the double-gated vertical array transistors. Area enhancement techniques in the trench capacitor allow the use of conventional dielectric materials into the 110 nm generation. A 512Mb prototype chip has been fabricated using this technology. |
来源出版物 | 2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS |
出版年 | 2002 |
页码 | 52-53 |
ISBN | 0-7803-7312-X |
出版者 | IEEE |
类型 | Proceedings Paper |
语种 | 英语 |
国家 | USA |
收录类别 | CPCI-S |
WOS记录号 | WOS:000176856300019 |
WOS类目 | Engineering, Electrical & Electronic ; Physics, Condensed Matter |
WOS研究方向 | Engineering ; Physics |
资源类型 | 会议论文 |
条目标识符 | http://119.78.100.177/qdio/handle/2XILL650/293655 |
作者单位 | (1)IBM Corp, Microelect, Semicond R&D Ctr, Hopewell Jct, NY 12533 USA |
推荐引用方式 GB/T 7714 | Akatsu, H,Weis, R,Cheng, K,et al. A highly manufacturable 110nm DRAM technology with 8F(2) vertical transistor cell for 1Gb and beyond[C]:IEEE,2002:52-53. |
条目包含的文件 | 条目无相关文件。 |
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