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| Performance enhancement techniques for low power digital phase locked loops | |
| Elshazly;Amr | |
| 出版年 | 2012 |
| 英文摘要 | Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. Graduation date: 2013 Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014 |
| 英文关键词 | Phase locked loops Delay locked loops Supply noise mitigation Background calibration Digital PLL Supply noise Time to digital converter TDC Switched ring oscillator SRO-TDC Digital circuits Low power Area efficient Digitally controlled oscillator Performance enhancement techniques Integrated circuits Frequency synthesizers Clock multipliers Integrated circuits Microelectronics Analog and mixed Circuits and systems Analog Digital Solid state circuit Phase-locked loops Electronic noise -- Prevention Low voltage systems Frequency synthesizers |
| 语种 | 英语 |
| URL | http://hdl.handle.net/1957/31116 |
| 资源类型 | 学位论文 |
| 条目标识符 | http://119.78.100.177/qdio/handle/2XILL650/246633 |
| 推荐引用方式 GB/T 7714 | Elshazly;Amr. Performance enhancement techniques for low power digital phase locked loops[D],2012. |
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